[
Date Prev][
Date Next][
Thread Prev][
Thread Next][
Date Index][
Thread Index]
[
List Home]
Re: [dsdp-dd-dev] Memory view and addressable size
|
Hi John -
I am curious about how the user knows what the correct addressable size is
when reading memory from different locations?
Is there some sort of spec that the user knows about? Or is it something
provided by the back-end on the fly?
To make sure that I understand this correctly, the reason why the Registers
View knows how to do the "right" thing is because the Registers View knows
the type of data that it is showing and knows how to read the data
correctly. For the Memory View, it's just a big chunk of memory, and there
is no way for the view / back-end to know how to read that memory because
we no longer have that information? As a result, we need to provide some
ways for the user to specify the size of the addressable units? Also, users
can look at the same memory with different addressable unit size
specifications and they would get different results?
Is it correct to say that you need support for a memory block that has
variable addressable size?
Thanks...
Samantha
John Cortell
<john.cortell@fre
escale.com> To
Sent by: Device Debugging developer
dsdp-dd-dev-bounc discussions
es@xxxxxxxxxxx <dsdp-dd-dev@xxxxxxxxxxx>,
dsdp-dd-dev@xxxxxxxxxxx
cc
06/21/2006 05:42
PM Subject
Re: [dsdp-dd-dev] Memory view and
addressable size
Please respond to
Device Debugging
developer
discussions
<dsdp-dd-dev@ecli
pse.org>
At 04:37 PM 6/21/2006, Daniel Jacobowitz wrote:
>On Wed, Jun 21, 2006 at 04:16:29PM -0500, John Cortell wrote:
> > At 03:42 PM 6/21/2006, Daniel Jacobowitz wrote:
> > >OK, that's what I had in mind and was interested in. I still think we
> > >could do this without user interface for it (by providing those two as
> > >"different" memory mapped registers, and the memory mapped register
> > >description indicating the access width), but that's much weaker than
> > >"there's always one right answer".
> >
> > That's fine for a register view, but it doesn't apply to the memory
> > view, right?
>
>I would speculate that if you have a memory view window pointed at a
>bank of MMIO registers, you may already be in bad straits. A
>significant portion of MMIO registers are active on read.
Well, yes, but MMIO is just one type of MMR.
BTW, the context for my inquiry was strictly the memory view
window. For other views (registers), I believe the debugger backed
can just "do the right thing" based memory configuration and register
description files.
John
_______________________________________________
dsdp-dd-dev mailing list
dsdp-dd-dev@xxxxxxxxxxx
https://dev.eclipse.org/mailman/listinfo/dsdp-dd-dev