Bug 566756 - Can not disassembly "sdiv" instruction correctly on arm cortex-a15
Summary: Can not disassembly "sdiv" instruction correctly on arm cortex-a15
Status: RESOLVED FIXED
Alias: None
Product: TCF
Classification: Tools
Component: Agent (show other bugs)
Version: unspecified   Edit
Hardware: PC Linux
: P3 normal (vote)
Target Milestone: 1.7   Edit
Assignee: Project Inbox CLA
QA Contact: Eugene Tarassov CLA
URL:
Whiteboard:
Keywords:
Depends on:
Blocks:
 
Reported: 2020-09-08 02:12 EDT by Mingfeng Liu CLA
Modified: 2021-06-25 16:24 EDT (History)
0 users

See Also:


Attachments
dkm file (154 bytes, text/plain)
2020-09-08 02:12 EDT, Mingfeng Liu CLA
no flags Details
dkm (5.55 KB, application/octet-stream)
2020-09-08 02:13 EDT, Mingfeng Liu CLA
no flags Details

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Description Mingfeng Liu CLA 2020-09-08 02:12:13 EDT
Created attachment 284074 [details]
dkm file

When debugging "start" function of attached "dkm.c" in Instruction Stepping Mode,
Disassembly view shows ".word 0xe710f110" for "SDIV r0,r0,r1" instruction.
<Disassembly view>
{
start:
009700bc: sub sp, sp, #8
009700c0: mov r0, #100
7 long tmp1 = 100, tmp2 = 200;
009700c4: str r0, sp, #+4
009700c8: mov r0, #200
009700cc: str r0, [sp]
9 tmp1 = tmp2 / tmp1;
009700d0: ldr r0, [sp]
009700d4: ldr r1, sp, #+4

009700d8: .word 0xe710f110 <-- ???

009700dc: str r0, sp, #+4
11 return (tmp1);
009700e0: ldr r0, sp, #+4
009700e4: add sp, sp, #8
009700e8: bx lr

but objdumparm show the correct
 d8:   e710f110        sdiv    r0, r0, r1
Comment 1 Mingfeng Liu CLA 2020-09-08 02:13:13 EDT
Created attachment 284075 [details]
dkm
Comment 2 Eugene Tarassov CLA 2020-09-14 18:05:27 EDT
Fixed.
Thanks!