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Re: [cdt-dev] Memory view and monitor
  • From: <Anton.Krug@xxxxxxxxxxxxx>
  • Date: Wed, 29 Jan 2020 18:15:09 +0000
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  • Thread-topic: [cdt-dev] Memory view and monitor
Yes, I might be overlapping two similar, but different problems.

  1. I will retest the 'mem 0 0 rw' without a peripheral view. And see if the regular memory view works.
  2. And then check my peripheral spec again if I did describe it correctly. To see if the mem-mapped peripherals work.
From: Liviu Ionescu <ilg@xxxxxxxxxx>
Sent: 29 January 2020 18:09
To: Anton Krug - M31845 <Anton.Krug@xxxxxxxxxxxxx>
Cc: cdt-dev@xxxxxxxxxxx <cdt-dev@xxxxxxxxxxx>
Subject: Re: [cdt-dev] Memory view and monitor
 
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> On 29 Jan 2020, at 19:28, <Anton.Krug@xxxxxxxxxxxxx> <Anton.Krug@xxxxxxxxxxxxx> wrote:
>
> It doesn't work on other peripherals, because that CoreTimer is the only peripheral I modeled for our RISC-V target.
> Under 'breaking it' I mean the peripheral is designed to be accessed in 32-bit mode and so does the simulated model of the peripheral, however in the simulated model I broke the spec and allowed it to be accessed in 8-bit chunks as well, then the peripheral view works as shown in the screenshot.

If the SVD defines the registers as 32-bit, and you see 8-bit accesses, then you probably hit a bug in the GME peripheral registers viewer, I don't think it has to do with CDT.


Regards,

Liviu

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